Semiconductor device designers often desire to increase the level of integration or density of features within a semiconductor device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, semiconductor device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.
One example of a semiconductor device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many types of memory including, but not limited to, random-access memory (RAM), read only memory (ROM), dynamic random access memory (PRAM), synchronous dynamic random access memory (SDRAM), flash memory, and resistance variable memory. Nonlimiting examples of resistance variable memory include resistive random access memory (ReRAM), conductive bridge random access memory (conductive bridge RAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin-torque-transfer random access memory (STTRAM), oxygen vacancy-based memory, and programmable conductor memory.
A typical memory cell of a memory device includes one access device, such as a transistor, and one memory storage structure, such as a capacitor. Modern applications for semiconductor devices can employ significant quantities of memory cells, arranged in memory arrays exhibiting rows and columns of the memory cells. The memory cells may be electrically accessed through digit lines (e.g., bit lines) and word lines (e.g., access lines) arranged along the rows and columns of the memory cells of the memory arrays. Memory arrays can be two-dimensional (2D) so as to exhibit a single deck (e.g., a single tier, a single level) of the memory cells, or can be three-dimensional (3D) so as to exhibit multiple decks (e.g., multiple levels, multiple tiers) of the memory cells.
Control logic devices within a base control logic structure underlying a memo array of a memory device have been used to control operations (e.g., access operations, read operations, write operations) on the memory cells of the memory device. An assembly of the control logic devices may be provided in electrical communication with the memory cells of the memory array by way of routing and interconnect structures. However, as the number of memory cells and a corresponding number of decks of a 3D memory array increases, electrically connecting the memory cells of the different decks of the 3D memory array to the assembly of control logic devices within the base control logic structure located below the memory array can create sizing and spacing complications associated with the increased quantities and dimensions of routing and interconnect structures required to facilitate the electrical connection. In addition, the quantities, dimensions, and arrangements of the different control logic devices employed within the base control logic structure can also undesirably impede reductions to the size of a memory device, increases to the storage density of the memory device, and/or reductions in fabrication costs.
It would, therefore, be desirable to have improved semiconductor devices, control logic assemblies, and control logic devices facilitating higher packing densities, as well as methods of forming the semiconductor devices, control logic assemblies, and control logic devices.